Digital Design Manager
Job Description
**About OLIX**
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten\-year\-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX\-1\) is the first accelerator architected specifically for decode. Rack\-scale co\-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
**Role:**
We’re searching for an ASIC Digital Design Manager to lead and deliver the digital subsystems of our next\-generation high\-speed mixed\-signal ASICs. This is a hands\-on leadership role with a strong focus on execution speed, first\-time\-right delivery, people management, and cross\-functional alignment. You will drive your team to deliver complex digital systems that integrate high\-bandwidth interfaces, deterministic control loops, and advanced mixed\-signal blocks—on schedule, on budget, and with uncompromising quality. As both a leader and technical authority, you will mentor engineers, set a high bar for performance, and ensure the program executes with precision from concept through tape\-out to mass production.
**Responsibilities:**
* Execution Ownership \& Speed – Lead end\-to\-end delivery of digital subsystems (RTL, synthesis, DFT/DFD, timing closure, physical implementation), ensuring aggressive schedule targets are met without compromising quality.
* Right\-First\-Time Delivery – Build and enforce processes that prioritize robust design, rigorous verification, and silicon bring\-up strategies that achieve first\-silicon success. Line \&
* Performance Management – Manage, mentor, and grow a high\-performing team of 6–12 digital engineers. Own goal\-setting, performance reviews, career development, and hiring, while fostering a culture of accountability and continuous improvement. Cross\-Functional
* Alignment – Drive seamless collaboration across analog, verification, layout, packaging, firmware, and test teams to keep programs moving fast and aligned from architecture spec implementation sign\-off bring\-up.
* Program Leadership – Define and track aggressive schedules, resource plans, and risk\- mitigation strategies. Communicate progress, trade\-offs, and escalation paths clearly to executives and customers.
* Technical Direction – Provide architectural and implementation guidance for high\-speed digital subsystems, including multi\-lane data paths, clocking, and mixed\-signal control loops.
* Culture of Speed \& Quality – Champion design automation, streamlined methodologies, and knowledge sharing to deliver high\-quality silicon on tight timelines.
**Skills \& Experience**
* 10\+ years of digital ASIC development, with at least 3 full product cycles successfully executed from specification to high\-volume production.
* Proven track record of driving on\-time, first\-time\-right delivery of complex, high\- performance ASICs with mixed\-signal interfaces (e.g., SerDes, DACs/ADCs, RF SoCs, display/camera pipelines).
* Strong expertise in RTL design (SystemVerilog/Verilog), CDC/RDC, STA, synthesis, P\&R, power intent (UPF/CPF), and DFT/DFD methodologies.
* Deep understanding of mixed\-signal interaction (coupling, jitter, supply noise, calibration) and ability to partner effectively with analog teams on specification splits.
* Demonstrated success in line management and performance management, including hiring, mentoring, and building high\-performing engineering teams.
* Skilled in fast\-paced, cross\-functional program leadership with a proven ability to manage schedules, risks, and vendor/foundry relationships.
* Outstanding written and verbal communication; confident presenting clear, concise program and technical status to executives, customers, and cross\-site teams.
**Compensation \& Equity**
* Competitive Salary: $388,000\+, commensurate with your experience, skills, and location.
* Equity \& Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it.
* Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer a $36k annual Living\-Local Bonus if your residence is within 20 minutes of the office.
**Time Off**
* Time Off: 33 days of paid time off (PTO), including US federal holidays.
**Health \& Wellbeing**
* Healthcare Coverage: Multiple high\-quality medical plan options, including family coverage.
* Health Savings Account: A high\-deductible medical option with a company\-funded health savings account (HSA).
* Dental \& Vision: Dental and vision coverage.
* Additional Coverage: Life insurance, plus short\- and long\-term disability.
* Wellbeing Support: Mental health resources, fertility
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten\-year\-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX\-1\) is the first accelerator architected specifically for decode. Rack\-scale co\-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
**Role:**
We’re searching for an ASIC Digital Design Manager to lead and deliver the digital subsystems of our next\-generation high\-speed mixed\-signal ASICs. This is a hands\-on leadership role with a strong focus on execution speed, first\-time\-right delivery, people management, and cross\-functional alignment. You will drive your team to deliver complex digital systems that integrate high\-bandwidth interfaces, deterministic control loops, and advanced mixed\-signal blocks—on schedule, on budget, and with uncompromising quality. As both a leader and technical authority, you will mentor engineers, set a high bar for performance, and ensure the program executes with precision from concept through tape\-out to mass production.
**Responsibilities:**
* Execution Ownership \& Speed – Lead end\-to\-end delivery of digital subsystems (RTL, synthesis, DFT/DFD, timing closure, physical implementation), ensuring aggressive schedule targets are met without compromising quality.
* Right\-First\-Time Delivery – Build and enforce processes that prioritize robust design, rigorous verification, and silicon bring\-up strategies that achieve first\-silicon success. Line \&
* Performance Management – Manage, mentor, and grow a high\-performing team of 6–12 digital engineers. Own goal\-setting, performance reviews, career development, and hiring, while fostering a culture of accountability and continuous improvement. Cross\-Functional
* Alignment – Drive seamless collaboration across analog, verification, layout, packaging, firmware, and test teams to keep programs moving fast and aligned from architecture spec implementation sign\-off bring\-up.
* Program Leadership – Define and track aggressive schedules, resource plans, and risk\- mitigation strategies. Communicate progress, trade\-offs, and escalation paths clearly to executives and customers.
* Technical Direction – Provide architectural and implementation guidance for high\-speed digital subsystems, including multi\-lane data paths, clocking, and mixed\-signal control loops.
* Culture of Speed \& Quality – Champion design automation, streamlined methodologies, and knowledge sharing to deliver high\-quality silicon on tight timelines.
**Skills \& Experience**
* 10\+ years of digital ASIC development, with at least 3 full product cycles successfully executed from specification to high\-volume production.
* Proven track record of driving on\-time, first\-time\-right delivery of complex, high\- performance ASICs with mixed\-signal interfaces (e.g., SerDes, DACs/ADCs, RF SoCs, display/camera pipelines).
* Strong expertise in RTL design (SystemVerilog/Verilog), CDC/RDC, STA, synthesis, P\&R, power intent (UPF/CPF), and DFT/DFD methodologies.
* Deep understanding of mixed\-signal interaction (coupling, jitter, supply noise, calibration) and ability to partner effectively with analog teams on specification splits.
* Demonstrated success in line management and performance management, including hiring, mentoring, and building high\-performing engineering teams.
* Skilled in fast\-paced, cross\-functional program leadership with a proven ability to manage schedules, risks, and vendor/foundry relationships.
* Outstanding written and verbal communication; confident presenting clear, concise program and technical status to executives, customers, and cross\-site teams.
**Compensation \& Equity**
* Competitive Salary: $388,000\+, commensurate with your experience, skills, and location.
* Equity \& Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it.
* Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer a $36k annual Living\-Local Bonus if your residence is within 20 minutes of the office.
**Time Off**
* Time Off: 33 days of paid time off (PTO), including US federal holidays.
**Health \& Wellbeing**
* Healthcare Coverage: Multiple high\-quality medical plan options, including family coverage.
* Health Savings Account: A high\-deductible medical option with a company\-funded health savings account (HSA).
* Dental \& Vision: Dental and vision coverage.
* Additional Coverage: Life insurance, plus short\- and long\-term disability.
* Wellbeing Support: Mental health resources, fertility
Posted: 2026-04-30